module cla_16 (A,B,Cin,invA,invB,sign,Out,Cout,Ofl,Zero);

	input [15:0] A,B;
	input Cin,invA,invB,sign;
	output [15:0] Out;
	output Cout,Ofl,Zero;

	wire n1,n2,n3;
	wire [3:0] cin_bus,cout_bus;
	cla_4 U0 (.A(A[3:0]),.B(B[3:0]),.Cin(Cin),.invA(invA),.invB(invB),
		.Out(Out[3:0]),.Cout(n1));
	cla_4 U1 (.A(A[7:4]),.B(B[7:4]),.Cin(n1),.invA(invA),.invB(invB),
		.Out(Out[7:4]),.Cout(n2));
	cla_4 U2 (.A(A[11:8]),.B(B[11:8]),.Cin(n2),.invA(invA),.invB(invB),
		.Out(Out[11:8]),.Cout(n3));
	cla_4 U3 (.A(A[15:12]),.B(B[15:12]),.Cin(n3),.invA(invA),.invB(invB),
		.Out(Out[15:12]),.Cout(Cout));

	assign Ofl = sign?(U3.U0.n3?(~(A[15]|B[15])):(A[15]&B[15])):Cout;
	assign Zero = ~(|Out[15:0]);

	endmodule
